In fabricating microelectronic semiconductor devices and the like on a semiconductor wafer (substrate or chip), e.g., of silicon, to form an integrated circuit (IC), etc., various metal layers and insulation layers are provided in selective sequence on the wafer. To maximize device component integration in the available wafer area to fit more components in the same area, increased IC miniaturization is utilized. Reduced pitch dimensions are used for denser packing of components per very large scale integration (VLSI) technique, e.g., at sub-micron dimensions, i.e., below 1 micron or 1,000 nanometers (nm) or 10,000 angstroms (A).
A metal CMP process is known for providing a damascene (inlaid) pattern, i.e., an arrangement of closely spaced apart individual metal lines, e.g., of aluminum (Al), copper (Cu) or tungsten (W), unconnected to each other and disposed in a like arrangement of closely spaced apart trenches, in an insulation (oxide) layer, e.g., of silicon dioxide (SiO2), in the IC fabrication of a semiconductor wafer, e.g., of silicon (Si).
For instance, the wafer, e.g., a circular disc of about 8 inches (200 mm) diameter, has an aluminum layer disposed on the oxide layer to provide metal lines in the trenches of the oxide layer. The wafer is typically polished by a rotating polishing pad, e.g., of about 20 inches diameter, such as of polyurethane fibrous plastic sheeting material, e.g., at about 20–100 rpm, such as about 50 rpm, e.g., under a polishing pressure downforce of about 2–8 psi, such as about 5 psi, e.g., for a polishing time of about 35–350 seconds, such as about 160 seconds, to an extent for forming the metal lines as individual lines in the trenches.
The metal CMP is effected while feeding onto the polishing pad an aqueous slurry of colloidal abrasive polishing particles, e.g., of alumina (Al2O3), and an associated oxidizer in water, e.g., at a flow rate of about 100–300 sccm (standard cubic centimeters per minute), such as about 200 sccm.
As the polishing progresses, the layer material being polished is locally incrementally removed, i.e., by chemical etching and mechanical abrasion, with the generation of debris constituting a concomitant CMP residue comprising a mixture of solid fine particles and liquid reaction products. The fine particles of the polishing debris or residue are traceable to the attendant metal layer material, insulation layer material and/or abrasive polishing particle material, and are generally fractured colloidal particles that are abrasive in nature. The liquid reaction products are traceable to the oxidizer and include chemical substances that are etchant in nature and prone to layer material etching.
After the metal CMP is completed, the wafer typically undergoes a water polishing step to remove the concomitant CMP residue. Then, the CMP operation is repeated for the next wafer. However, some of the concomitant CMP residue accumulates incrementally on the polishing pad, e.g., of polyurethane fibrous plastic sheeting material, during the CMP operation for each wafer, which progressively increasingly loads the polishing pad with such CMP residue despite the water polishing step applied to each wafer after it has been subjected to metal CMP.
Typically, each of a plurality of wafers, e.g., 25 wafers, comprising a first lot, is subjected respectively to the metal CMP operation (including the water polishing step), followed by a further plurality of wafers, e.g., 25 more wafers, comprising a second lot, and then a still further plurality of wafers, e.g., 25 additional wafers, comprising a third lot. After 3 such lots of wafers, e.g., 75 wafers, have been processed in succession, the concomitant CMP residue loaded polishing pad is normally replaced by a fresh (clean) polishing pad, and the next cycle of 3 lots is subjected to the metal CMP operation.
Experience has shown that at most about 3 lots of wafers, e.g., about 75 wafers, can be adequately polished by the same polishing pad because of the progressive incremental loading of concomitant metal CMP residue thereon. Indeed, for wafers of the same lot, it is recognized that the ones that are last to be polished suffer from more severe dishing and erosion than the earlier ones, given the progressive increase of such metal CMP residue loading on the polishing pad and its abrasive and etchant effects on the wafers.
In particular, the so-polished wafers usually suffer from attendant dishing in the damascene pattern area containing the metal lines in the trenches, plus erosion of adjacent portions of the oxide layer. Dishing is the formation of a concave depression, e.g., in the arrangement of metal lines in the trenches, which occurs during metal CMP. Erosion is the associated non-uniform (uneven) removal of, e.g., oxide, layer material, locally or globally, which also occurs during the metal CMP operation.
Dishing adversely affects the sheet resistance (RS) performance of each metal line. In this regard, RS, for a given width of metal line, is the quotient of the resistivity of the metal material divided by the metal line thickness (height) and is a measure of the amount of current the line can carry. Such metal line height decreases as the dishing depth increases. The smaller the metal line cross sectional area, the smaller the current the line can carry. Thus, dishing during metal CMP results in undesired high resistivity of the eventual metal structure produced.
Erosion adversely affects the performance characteristics of subsequent (higher) metallization levels. Erosion introduces non-planarity onto the wafer surface which results in difficultly removable metal puddles consequent metallization operations at higher levels, and can cause electrical shorting between adjacent metal lines, e.g., in an upper level damascene arrangement.
It is desirable to have a metal CMP process for forming closely spaced apart metal lines as individual metal lines in trenches in an insulation layer of each of a plurality of semiconductor wafers, which minimizes (reduces) resultant dishing and erosion, without requiring additional consumable materials beyond those normally used and without significantly reducing wafer throughput or product yield.